The present invention relates to semiconductor devices, and methods of manufacturing semiconductor devices, including various circuits and electronic devices.
As a semiconductor device, there has been widely used a memory such as a flash memory which is comprised of floating gate and control gate. A memory cell serving as a smallest unit may include a tunnel oxide film (a first insulating film) formed by oxidizing the surface of a semiconductor substrate, a floating gate (a first poly-silicon film) formed on the tunnel oxide film, a dielectric film (a second insulating film) formed on the floating gate, and a control gate (a second poly-silicon film) formed on the dielectric film. Further, a semiconductor substrate is formed with a source area and a drain area under the tunnel oxide film, and the two areas are located on such positions that the floating gate is interposed therebetween. One (a first impurity area) of the source area and the drain area is connected through a connecting area (a third impurity area) to one (a second impurity area) of the source area and the drain area of an adjacent area.
Here, there is a problem that can be described as follows, i.e., if the third impurity area is formed at the same time as the above first and second impurity areas in accordance with a depth and a impurity concentration required by the first and second impurity areas, the resistance of the connecting area (the third impurity area) will become high, hence retarding the transmission of a signal.
Certain embodiments relate to a method of manufacturing a semiconductor device, including a laminating step including forming tunnel insulating films, floating gates, dielectric films and control gates on first and second cell areas, the first and second cell areas being formed mutually adjacent to each other on a semiconductor substrate. A plurality of impurity area formation steps are carried out for forming sources and drains on the first and second cell areas. The method also includes forming an electric connection between one of the source and drain of the first cell area and one of the source and drain of the second cell area. The electrical connection may flow through a connecting area formed to have a lower electric resistance than impurity areas formed in one of the plurality of impurity area formation steps.
Other embodiments relate to a semiconductor device including tunnel insulating films, floating gates, dielectric films and control gates, all of which are formed on first and second cell areas on a semiconductor substrate. Sources and drains are formed on the first and second cell areas, and a connecting area is formed that is capable of electrically connecting one of the source and drain of the first cell area with one of the source and drain of the second cell area. The connecting area is formed to have an electric resistance which is lower than any one of the sources and drains of the first and second cell areas.
Other embodiments relate to a method for manufacturing a semiconductor device, including forming first and second field effect transistors, each having source/drain regions, and forming a conducting region connecting a source/drain region of the first field effect transistor to a source/drain region of the second field effect transistor, wherein the conducting region is formed to have a lower resistance than at least one of the source/drain regions.
Other embodiments relate to a semiconductor device including first and second field effect transistors, each having source/drain regions, and a conducting region connecting a source/drain of the first field effect transistor to a source/drain of the second field effect transistor, the conducting region having a lower resistance than at least one of the source/drain regions.
Still other embodiments relate to a semiconductor device including first and second memory cell means for storing data, the first and second memory cell means including source/drain regions. The device also includes connecting means for electrically connecting the first and second memory cell means, the connecting means having a resistance lower than that of the source/drain regions.